Random Access Memory (RAM) is a type of data storage that a computer processor can quickly access. It consists of an array of addressable storage cells that each stores bit(s) of information (either a zero or one per bit).
The currently prevalent RAM types fall into two general categories, static and dynamic. The storage unit of a static RAM (SRAM) cell is typically a bi-stable flip-flop whose state indicates the stored value. The storage unit of a dynamic RAM (DRAM) cell is typically an integrated circuit capacitor whose charge indicates the stored value. Because the capacitor leaks charge, DRAM requires control circuitry to “refresh” the stored data by reading each cell's stored value and writing it back. This refresh operation occurs as often as every few milliseconds. DRAM can structurally achieve a higher memory density than SRAM; therefore, it is cheaper and has broader applications in volatile memory.
The 1T1C DRAM cell is the current industry standard due to its simplicity and small size. Successive DRAM generations have gradually reduced the cell size by shrinking the transistor, thereby achieving higher memory densities and lower production costs. However, since the 1 Mb DRAM generation in the mid-1980's, the capacitor has been forced to assume increasingly complicated 3-dimensional structures to store enough charges for a given cell size. While variations on memory design have replaced the capacitor with an alternate secondary storage unit such as a resistor, magnetic tunnel junction (MTJ), etc., the presence of a secondary component has limited continued scalability.
While early MOS memory was originally a stand-alone component within the computer, recent memory development has focused on the integration of memory and logic on a single chip—a feat that allows for improved performance, lower power consumption, less board space requirements, and reduced number of chips, among other advantages. While SRAM is widely used as an embedded memory, it is subject to standby power dissipation and increased susceptibility to soft errors. Embedded DRAM can bypass these challenges and also allow for higher memory densities; however, the presence of the capacitor in existing DRAM designs has made it more difficult to integrate with standard CMOS processes.
FeFET-based memory may be used to perform the functions of DRAM (as illustrated in U.S. Pat. No. 6,067,244 to Ma [hereinafter “MA ‘244’”], the disclosure of which is hereby incorporated by reference in its entirety) as well as non-volatile memory (as illustrated in U.S. Pat. No. 5,198,994 to Natori, the disclosure of which is hereby incorporated by reference in its entirety). FIG. 4 presents the architecture of a typical FeFET cell, with the ferroelectric field effect transistor (FET) as its fundamental storage unit. Because the FeFET memory cells lack a capacitor or other secondary storage component, it is suitable for embedded applications and its size depends on only the transistor. FeFET memory also possesses a (1) long retention time that enables low refresh frequency and (2) a non-destructive read operation. The recent discovery of HfO2-based ferroelectrics has overcome the limitations of the state-of-the-art ferroelectric materials such as lead zirconate titanate (PZT) and strontium bismuth tantalate (SBT), making FeFET memory more suitable for commercial application.